Low cost prototyping and limited volume production are possible with Multi Project Wafer (MPW) services in which devices of different customers are fabricated in a single wafer run. Since multiple customers share the same mask set, the costs of mask making and fabrication are divided.

MPW processing

The microBUILDER project provides access to state-of-the-art MEMS technologies at SensoNor Technologies and TRONICS Microsystems. The MPW processes are fully documented in the microBUILDER design handbook. Customers have the choice to either use the microBUILDER services for designing a device or to design their own component. For this purpose, special training courses are provided.

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Features of the SensoNor Technologies MPW process

The MultiMEMS MPW process offers buried conductors and piezoresistors, thin silicon diaphragms, cantilevers and channels as well as glass and silicon cavities in a triple-stack anodic bonded configuration.

Chip size 3 x 3 mm², 3 x 6 or 6 x 3  mm², or 6 x 6 mm²

• Minimum feature size 2 µm
• High-volume approach to production
• High-precision membrane definition by etch stop against pn-junctions
• High aspect ratio RIE
• High stability piezoresistors for sensing elements
• Triple-stack Glass/Si/Glass anodically bonded
• Hermetically sealed cavities with electrical feed-throughs
• Thermal excitation / Piezoresistive detection

Schematic outline of the Infineon SensoNor MPW process

Schedule for the Infineon SensoNor MPW process

Reservation for a MPW run can be made by submitting the request form.
*The MultiMEMS MPW service will be discontinued on 30 October, 2009

Costs for the SensoNor MPW run

 
The costs are per project and includes the fabrication and the shipping of at least 100 dies for each submitted project. Customers which submit more than two projects for the same MPW run are eligible for discounts. Discounts may also be offered to returning customers.

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Features of the TRONICS Microsystems process

The TRONICS MPW process provides silicon channels, mixing pillars, heating electrodes and impedance sensing electrodes.

• Chip size 8 x 7 mm²
• Minimum feature size 4 µm
• Minimum gap size 3 µm
• SOI-HARM (High Aspect Ratio Micromachining), aspect ratio > 1:20
• Si-DRIE/Glass under development

Schematic outline of the Tronics process

Schedule for the Tronics MPW process, running three times each year

Costs for the Tronics MPW run. For each location Tronincs deliver 20 chips